岗位描述

The High Energy Efficiency Chip design group is looking for a talented and enthusiastic Logic Designer intern to join our growing team and take part in developing state-of-the-art products. You will have chance to be working with the latest silicon technologies and processes to build the most advanced large-scale complex designs. As part of this role, you will join the full development cycles of design units from architecture to tape-out. And work in full collaboration with the architecture, validation, Backend, IC operation, Software, and ASIC teams.
Join us and contribute to our growing success in the High Energy Efficiency world.

Responsibilities for Chip design engineer Intern：
- Participate in IP selection and architecture definition, formulate functional specifications.
- Developing functional block/unit RTL for architectural features and optimizing for power, area, and timing
- Perform all aspects of design flow from logic synthesis, power, timing, quality checks
- Support verification engineer to fix case, meet design requirements at each milestone and support tape-out.

Kindly note that:
- Applications are assessed on a rolling-basis.
- The specific dates and duration of internship is open to further discussion with successful applicants.

任职要求

- M.S./B.S. Prefer in Electrical Engineering or Microelectronics, relevant major.
- Hands-on experience or Proficient in RTL design using Verilog/System Verilog
- Design Experience with logic FE tools(Synopsys: spyglass,vcs,verdi) - advantage.
- Knowledge in Physical Design & Static Timing Analysis knowledge or experience is a PLUS
- Prefer experience with low-power design
- Proficiency in Tcl, Perl, Python is a PLUS

立即申请