Job Description

The High Energy Efficiency Chip verification group is looking for a talented and enthusiastic Chip Verification Designer to join our growing team and take part in developing state-of-the-art products.

In this role, you will have chance to perform functional verification of logic to ensure design will meet specification requirements. You will also develop verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. In addition, you will execute verification plans and define and run system simulation models to verify the design, analyze power and timing, and uncover bugs. You will collaborate with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.

Responsibilities for Chip verification engineer Intern：
- Undertake chip verification work for new products
- Participate in IP and system-level simulation verification.
- Based on architectural documentation, construct a verification environment using UVM. And env maintenance.
- Define rational functional coverage targets, Improve code coverage and functional coverage base-on verification plan.
- Cover for gate-level-simulation and post-level-simulation
- Case fix, complete verification tasks at each deliver stage, meet validation requirements at each milestone and support tape-out.

Kindly note that:
- Applications are assessed on a rolling-basis.
- The specific dates and duration of internship is open to further discussion with successful applicants.

Internship Requirements

- M.S./B.S. Prefer in Electrical Engineering or Microelectronics, relevant major.
- Knowledge in UVM methodology - advantage.
- Hands-on experience in verilog/System Verilog
- Proficient in python/perl/tcl/shell - advantage
- Fundamental knowledge in semiconductor process is preferred

Apply now